The present invention relates to semiconductor integrated circuits and, more particularly, to the fabrication of integrated circuits requiring deep implant of impurities.
With increasing levels of integration in semiconductor chips or dies in a wafer, such as those with a silicon substrate, greater demands on the method of fabricating the semiconductor chips, such as making deep implant of impurities into the semiconductor substrate. Deep implantation at higher dosage is required to stop leakage effects and for higher performance and increased density. However, as the layout of the integrated circuit positions the transistors, parts of the transistor and other components of the circuit closer and closer together, it becomes increasing difficult to perform a deep implant step in the fabrication method in one area of the layout with encroaching on an adjacent area and effecting the required parameters of that area. Since the layout of the integrated circuit will continue to shrink, this problem will become even more critical in future generations of integrated circuits.
During deep implantation, the impurities being implanted, which are shown as arrows in FIGS. 2 and 3 representing the prior art, scatter in the implant mask, such as photoresist. The mask is used to protect the other areas of the integrated circuit which are not intended to be implanted with impurities during this implantation step. However, at the edges of the implant mask, as shown in FIG. 3, some of the implanted impurities scatter out of the implant mask and into the unmasked areas of the wafer. This undesirable scattering of impurities into adjacent unmasked areas of the wafer will affect the performance of the fabricated integrated circuit and lower the manufacturing yield of the integrated circuits chips in a wafer.
Thus, with increasing density of integrated circuits, especially integrated circuits requiring deep implants of impurities, it is critical to have a fabrication process which is will overcome this scattering of the impurities into substrate areas adjacent to the implant masked areas. Accordingly, it is an object of the present invention to design a process for fabricating an integrated circuit chip requiring deep implants of impurities which prevents the impurities from scattering into substrate areas adjacent to the implant masked areas. In addition, it is an object of the present invention to provide a simple modification to the prior art method of deep implantation, which will not impact the throughput of the prior art deep implant process and which will not complicate the overall fabrication of the integrated circuit chip. Further, it is object of the present invention to provide a simple modification such that the prior art process steps following the deep implant step will not be substantially affected by the modification.
To achieve these and other objects, a fabrication process of the present invention for preventing scattering of impurities from masked layer into substrate areas adjacent to the masked area during a deep implant, a thin, easily removable, scattered impurity capturing layer is present in the areas adjacent the implant masked areas to capture the scattered impurities and prevent them from reaching the wafer substrate. Preferably, the layer is an anti-reflecting coating (ARC) which normally is positioned beneath a photoresist and is well known in the art for preventing UV light used in exposing the photoresist from being reflected back from the surface of the wafer. However, in the present invention, the ARC is not used for that purpose and its function is to capture scattered impurities and not prevent reflected UV light. Although other materials can be used, such as a hard mask of a silicate glass, the advantage of the ARC is that it may be present during the exposure of the photoresist and, after selective removal the photoresist, it can remain and serve the new function of the present invention. It also is easily removed when its function of collecting scattered implanted impurities is finished.
Since the scattered implanted impurities contain in the range of one-third (⅓) to one-one hundredth ({fraction (1/100)}) the energy of the original impurities and are scattered at an angle and not normal to the wafer, the thickness of the capturing layer can range in thickness from one-third (⅓) to one fiftieth ({fraction (1/50)}) the depth of the deep implanted impurities.
Although the present invention of using a scattered impurity ion collection layer during deep implantion is highly-suited for forming N-wells and P-wells for a CMOS transistor, it also can be used for any deep implantion, such as highly doped source/drain and pocket/extension implants, collector, base and emitter implants for bipolar devices, barrier implants to separate a well from the substrate, implants for gate doping and implants to connect wells together.